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rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 sst-melody -dap audio processor features 16-bit fixed-point audio processor (dsp-based) decodes major standard audio formats using 16-bit fixed-point implementation for decoding: mpeg 1 layer i, ii, and iii (mp3) aac 2-channel low complexity microsoft wma speech codecs: mgsm, g.723.1, and audible audio 2 independent data address generators powerful program sequencer provides zero overhead looping conditional instruction execution program- mable 16-bit interval timer with prescaler 100-lead lqfp and 144-ball mini-bga supports postprocessing: jazz/rock/classic/pop/bass 3-band user customizable graphic equalizer supports major storage formats: smartmedia card dataplay sd card nand flash supports drm (digital rights management) technologies: liquid audio sp3 microsoft drm dataplay contentkey supports standard apis: start play stop play mute play resume play download song to flash forward to next song rewind to previous song delete a song bass/equalizer erase mp3 flash upload song/voice from flash rename flash start record stop record report get file information seek file list number of songs request song name list number of voices request voice note name start record (g.723.1) stop record (g.723.1) start play (g.723.1) stop play (g.723.1) (continued on page 2) functional block diagram or external databus internal dma port host mode full memory mode programmable i/o and flags timer power - down control memory program memory 16k 24 bit data memory 16k 16 bit serial ports sport1 sport0 program sequencer data address generators dag1 dag2 alu mac shifter arithmetic units adsp-2100 base architecture program memory address program memory data data memory data data memory address external address bus external databus byte dma controller
rev. 0 ?2? SST-MELODY-DAP mute play (voice) resume play (voice) download voice to flash forward to next record rewind to previous record delete a record erase voice flash version reporting (g.723.1) get g.723.1 record information rename voice file format flash volume control get song name get album name get singer name get song duration version reporting supports pc interface usb 1.1 interface parallel port interface other features: id3 tag support sdmi capable performance 13.3 ns instruction cycle time @ 2.5 v (internal) 75 mips sustained performance single-cycle instruction execution single-cycle context switch 3-bus architecture allows dual operand fetches in every instruction cycle multifunction instructions power-down mode featuring low cmos standby power dissipation with 200 clkin cycle recovery from power-down condition low power dissipation in idle mode integration adsp-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions 80 kbytes of on-chip ram, configured as 16k words program memory ram 16k words data memory ram dual-purpose program memory for both instruction and data storage independent alu, multiplier/accumulator, and barrel shifter computational units system interface flexible i/o structure allows 2.5 v or 3.3 v operation; all inputs tolerate up to 3.6 v regardless of mode 16-bit internal dma port for high speed access to on-chip memory (mode selectable) 4 mbyte memory interface for storage of data tables and program overlays (mode selectable) 8-bit dma to byte memory for transparent program and data memory transfers (mode selectable) i/o memory interface with 2048 locations supports parallel peripherals (mode selectable) programmable memory strobe and separate i/o memory space permits ?glueless? system design programmable wait state generation two double-buffered serial ports with companding hardware and automatic data buffering automatic booting of on-chip program memory from byte-wide external memory, e.g., eprom, or through internal dma port six external interrupts 13 programmable flag pins provide flexible system signaling uart emulation through software sport reconfiguration ice-port? emulator interface supports debugging in final systems ice-port is a trademark of analog devices, inc.
rev. 0 SST-MELODY-DAP ?3? features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional block diagram . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 4 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 instruction set description . . . . . . . . . . . . . . . . . . . . . . . . 4 recommended operating conditions . . . . . . . 4 electrical characteristics . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . 6 ordering information . . . . . . . . . . . . . . . . . . . . . . 6 100-lead lqfp pin configuration . . . . . . . . . . . . 6 pin function descriptions . . . . . . . . . . . . . . . . . . 7 timing specifications . . . . . . . . . . . . . . . . . . . . . . . 7 general notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 timing notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 memory timing specifications . . . . . . . . . . . . . . 8 frequency dependency for timing specifications . . . . . . . . . . . . . . . . . . . . . . . 8 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 output drive currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 capacitive loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 software architecture . . . . . . . . . . . . . . . . . . . . 10 architecture overview . . . . . . . . . . . . . . . . . . . . 10 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 common-mode pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 memory interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 full memory mode pins (mode c = 0) . . . . . . . . . . . . . . 13 host mode pins (mode c = 1) . . . . . . . . . . . . . . . . . . . . 13 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 low power operation . . . . . . . . . . . . . . . . . . . . . . . 15 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 slow idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 reset 1 p s 1 modes o operation 1 s m m 1 p c 1 a c 1 iack c 1 memor architectre 1 p m 1 d m 1 memory mapped registers (new to the SST-MELODY-DAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 i/o space (full memory mode) . . . . . . . . . . . . . . . . . . . . 20 composite memory select ( cms 20 b m s bms 20 b m 20 b m dma bdma m m 20 i m dma p idma p h m m 21 b l b 22 idma p b 22 b r b g 22 i/o p 22 otline dimensions 100l m t p q lqp st100 2 t t i m t s t ii e c t iii p d ex t i p t 1 t i p i a 1 t i m o 1 t ii pmola b 1 t iii dmola b 1 t i w s 20 t d 21 table o contents
rev. 0 ?4? SST-MELODY-DAP general description the SST-MELODY-DAP is a single-chip microcomputer opti- mized for digital signal processing (dsp) and other high speed numeric processing applications. the SST-MELODY-DAP combines the adsp-2100 family base architecture (three computational units, data address genera- tors, and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, extensive interrupt capabilities, and on-chip program and data memory. the SST-MELODY-DAP integrates 80 kbytes of on-chip memory configured as 16k words (24-bit) of program ram, and 16k words (16-bit) of data ram. power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. the SST-MELODY-DAP is available in a 100-lead lqfp package and 144-ball mini-bga. in addition, the SST-MELODY-DAP supports new instruc- tions, which include bit manipulations?it set, bit clear, bit toggle, bit test?ew alu constants, new multiplication instruction (x squared), biased rounding, result-free alu operations, i/o mem ory transfers, and global interrupt mask- ing, for increased flexibility. fabricated in a high speed, low power, cmos process, the SST-MELODY-DAP operates with a 13.3 ns instruction cycle time. every instruction can execute in a single processor cycle. the SST-MELODY-DAP? flexible architecture and comprehen- sive instruction set allow the processor to perform multiple operations in parallel. in one processor cycle, the sst-melody- dap can: ? generate the next program address ? fetch the next instruction ? perform one or two data moves ? update one or two data address pointers ? perform a computational operation this takes place while the processor continues to: ? receive and transmit data through the two serial ports ? receive and/or transmit data through the internal dma port ? receive and/or transmit data through the byte dma port ? decrement timer instruction set description the SST-MELODY-DAP assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. the assembly language, which takes full advantage of the processor? unique architecture, offers the following benefits: ? the algebraic syntax eliminates the need to remember cryptic assembler mnemonics. for example, a typical arithmetic add instruction, such as ar = ax0 + ay0, resembles a simple equation. ? every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. ? the syntax is a superset adsp-2100 family assembly lan- guage and is completely source and object code compatible with other family members. programs may need to be relo- cated to utilize on-chip memory and conform to the SST-MELODY-DAP? interrupt vector and reset vector map. ? sixteen condition codes are available. for conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. ? multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle. recommended operating conditions k grade b grade parameter min max min max unit v ddint 2.37 2.63 2.25 2.75 v v ddext 2.37 3.6 2.25 3.6 v v input v il = ?.3 v ih = +3.6 v il = ?.3 v ih = +3.6 v t amb 0 +70 ?0 +85 c specifications subject to change without notice. specifications
rev. 0 SST-MELODY-DAP ?5? electrical characteristics k/b grades parameter test conditions min typ max unit v ih hi-level input voltage 1, 2 @ v ddint = max 1.5 v v ih hi-level clkin voltage @ v ddint = max 2.0 v v il lo-level input voltage 1, 3 @ v ddint = min 0.7 v v oh hi-level output voltage 1, 4, 5 @ v ddext = min, i oh = ?.5 ma 2.0 v @ v ddext = 3.0 v, i oh = ?.5 ma 2.4 v @ v ddext = min, i oh = ?00 ma 6 v ddext ?0.3 v v ol lo-level output voltage 1, 4, 5 @ v ddext = min, i ol = 2 ma 0.4 v i ih hi-level input current 3 @ v ddint = max, v in = 3.6 v 10 a i il lo-level input current 3 @ v ddint = max, v in = 0 v 10 a i ozh three-state leakage current 7 @ v ddext = max, v in = 3.6 v 8 10 a i ozl three-state leakage current 7 @ v ddext = max, v in = 0 v 8 10 a i dd supply current (idle) 9 @ v ddint = 2.5, t ck = 15 ns 9ma @ v ddint = 2.5, t ck = 13.3 ns 10 ma i dd supply current (dynamic) 9 @ v ddint = 2.5, 15 ns 10 , t amb = 25 c 35 ma @ v ddint = 2.5, 13.3 ns 10 , t amb = 25 c 38 ma i dd supply current (power-down) 11 @ v ddint = 2.5, t amb = 25 c in lowest 100 a power mode c i input pin capacitance 3, 6 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf c o output pin capacitance 6, 7, 11, 12 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf notes 1 bidirectional pins: d0?3, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a1?13, pf0?f7 2 input only pins: reset , br , dr0, dr1, pwd . 3 input only pins: clkin, reset , br , dr0, dr1, pwd 4 output pins: bg , pms , dms , bms , ioms , cms , rd , wr , pwdack, a0, dt0, dt1, clkout, fl2?, bgh 5 although specified for ttl outputs, all adsp-2185m outputs are cmos compatible and will drive to v ddext and gnd, assuming no dc loads. 6 guaranteed but not tested 7 three-statable pins: a0?13, d0?23, pms , dms , bms , ioms , cms , rd , wr , dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rfs1, pf0?f7 8 0 v on br 9 i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunctional (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 10 v in = 0 v and 3 v. for typical figures for supply currents, refer to power dissipation section. 11 see chapter 9 of the adsp-2100 family user? manual (3rd edition, 9/95) for details. 12 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice.
rev. 0 ?6? SST-MELODY-DAP absolute maximum ratings 1 internal supply voltage (v ddint ) . . . . . . . . . ?.3 v to +3.0 v internal supply voltage (v ddext ) . . . . . . . . . ?.3 v to +4.0 v input voltage 2 . . . . . . . . . . . . . . . . . . . . . . . . ?.5 v to +4.0 v output voltage swing 3 . . . . . . . . . . ?.5 v to v ddext + 0.5 v operating temperature range . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature (5 sec) lqfp . . . . . . . . . . . . . . . . . . 280 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 applies to bidirectional pins (d0?3, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a1?13, pf0?f7) and input only pins (clkin, reset , br , dr0, dr1, pwd ) 3 applies to output pins ( bg , pms , dms , bms , ioms , cms , rd , wr , pwdack, a0, dt0, dt1, clkout, fl2?, bgh ) ordering information the analog devices SST-MELODY-DAP reference design must be ordered under the part number adsst-melody- sdk for the standalone reference design. this includes the evaluation board with an evaluation copy of the software and schematics. designers of products using this reference design also will be required to sign a license agreement with the respective license holder i.e., digital theater systems (dts), dolby labora- tories, thx ltd., microsoft, or srs labsto use the appropriate code and produce proof to analog devices of having successfully completed the appropriate licensing proce- dures before final products can be shipped to them. the final product will be shipped from analog devices and will include the decoder chipset and software; customers will be required to sign license agreements with analog devices and separately pay system royalties to the respective license holder. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the SST-MELODY-DAP features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device 100-lead lqfp pin configuration 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 25 a4/iad3 a5/iad4 gnd a6/iad5 a7/iad6 a8/iad7 a9/iad8 a10/iad9 a11/iad10 a12/iad11 a13/iad12 gnd clkin xtal v ddext clkout gnd v ddint wr rd bms dms pms ioms cms pin1 identiier 100 2 1 0 2 1 aiad2 a2iad1 a1iad0 a0 pw dack bgh p0modea p1modeb gnd pwd ddet p2modec pmoded l0 l1 l2 d2 d22 d21 d20 0 gnd d1 d1 d1 d1 2 0 1 1 2 0 1 2 d1 d1 d1 d12 gnd d11 d10 d ddet gnd d d iwr d ird dial d is gnd ddint d iack d2iad1 d1iad1 d0iad1 bg ebg br ebr 2 0 1 2 0 1 dt0 ts0 rs0 dr0 sclk0 ddet dt1o ts1 irq1 rs1 irq0 dr1i gnd sclk1 ereset reset ems ee eclk elot elin eint 2 2 2 0 2 irqe p irql0 p gnd irql1 p irq2 p topiew ns sstmdap
rev. 0 SST-MELODY-DAP C7C pin no. mnemonic 26 irqe +pf4 27 irql0 +pf5 28 gnd 29 irql1 +pf6 30 irq2 +pf7 31 dt0 32 tfs0 33 rfs0 34 dr0 35 sclk0 36 v ddext 37 dt1/fo 38 tfs1/ irq1 39 rfs1/ irq0 40 dr1/fi 41 gnd 42 sclk1 43 ereset 44 reset 45 ems 46 ee 47 eclk 48 elout 49 elin 50 eint pin no. mnemonic 1 a4/iad3 2 a5/iad4 3gnd 4 a6/iad5 5 a7/iad6 6 a8/iad7 7 a9/iad8 8 a10/iad9 9 a11/iad10 10 a12/iad11 11 a13/iad12 12 gnd 13 clkin 14 xtal 15 v ddext 16 clkout 17 gnd 18 v ddint 19 wr 20 rd 21 bms 22 dms 23 pms 24 ioms 25 cms pin no. mnemonic 51 ebr 52 br 53 ebg 54 bg 55 d0/iad13 56 d1/iad14 57 d2/iad15 58 d3/ iack 59 v ddint 60 gnd 61 d4/ is 62 d5/ial 63 d6/ ird 64 d7/ iwr 65 d8 66 gnd 67 v ddext 68 d9 69 d10 70 d11 71 gnd 72 d12 73 d13 74 d14 75 d15 pin no. mnemonic 76 d16 77 d17 78 d18 79 d19 80 gnd 81 d20 82 d21 83 d22 84 d23 85 fl2 86 fl1 87 fl0 88 pf3 [mode d] 89 pf2 [mode c] 90 v ddext 91 pwd 92 gnd 93 pf1 [mode b] 94 pf0 [mode a] 95 bgh 96 pwdack 97 a0 98 a1/iad0 99 a2/iad1 100 a3/iad2 the lqfp package pinout is shown in the pin function descriptions. pin names in bold text replace the plain text named function s when mode c = 1. a plus (+) sign separates two functions when either function can be active for either major i/o mode. signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of reset. the multiplexed pins dt1/fo, tfs1/ irq1 , rfs1/ irq0 , and dr1/fi are mode selectable by setting bit 10 (sport1 configure) of the system control register. if bit 10 = 1, these pins have serial port functionality. if bit 10 = 0, these pins are the extern al interrupt and flag pins. this bit is set to 1 by default upon reset. timing specifications general notes use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, the user cannot meaningfully add up parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. there is no control over this. timing circuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell what the processor will do in a given circumstance. switching characteris- tics may be used to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the proces- sor operates correctly with other devices. memory timing specifications table i shows common memory device specifications and the corresponding SST-MELODY-DAP timing parameters, for your convenience. pin function description
rev. 0 ?8? SST-MELODY-DAP assumptions: ? external data memory is accessed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? the application operates at v ddext = 3.3 v and t ck = 30 ns. total power dissipation = p int + ( c v ddext 2 f ) p int = internal power dissipation from power vs. frequency graph (see figures 2a through 2c). ( c v ddext 2 f ) is calculated for each output: table iii. power dissipation example n o. of c v ddext 2 f pd parameter pins (pf) (v) (mhz) (mw) address 7 10 3.3 2 16.67 12.7 data output, wr 910 3.3 2 16.67 16.6 rd 1 10 3.3 2 16.67 1.8 clkout, dms 210 3.3 2 33.3 7.2 total 38.2 total power dissipation for this example is p int + 38.0 mw. output drive currents figure 1 shows typical i? characteristics for the output drivers on the SST-MELODY-DAP. the curves represent the current drive capability of the output drivers as a function of output voltage. source voltage ?v ?0 0 source current ?ma 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ?0 ?0 ?0 0 20 40 60 80 v ddext ?3.6v @ ?0 c v ddext ?3.3v @ +25 c v ddext ?2.5v @ +85 c v oh v ol v ddext ?3.6v @ ?0 c v ddext ?2.5v @ +85 c v ddext ?3.3v @ +25 c figure 1. typical output driver characteristics table i. memory timing specifications memory timing device parameter specification parameter definition * address setup to t asw a0?13, xms setup write start before wr low address setup to t aw a0?13, xms setup write end before wr deasserted address hold t wra a0?13, xms h old time before wr low data setup time t dw data setup before wr high data hold time t dh data hold after wr high oe to data valid t rdd rd low to data valid address access t aa a0?13, xms to time data valid * xms = pms , dms , cms , or ioms . frequency dependency for timing specifications t ck is defined as 0.5 t cki . the SST-MELODY-DAP uses an input clock with a frequency equal to half the instruction rate. for example, a 37.50 mhz input clock (which is equivalent to 26.6 ns) yields a 13.3 ns processor cycle (equivalent to 75 mhz). t ck values within the range of 0.5 t cki period should be substituted for all relevant timing parameters to obtain the specification value. example: t ckh = 0.5 t ck ?2 ns = 0.5 (15 ns) ?2 ns = 5.5 ns table ii. environmental conditions * rating description symbol lqfp mini-bga thermal resistance ca 48 c/w 63.3 c/w (case-to-ambient) thermal resistance ja 50 c/w 70.7 c/w (junction-to-ambient) thermal resistance jc 2 c/w 7.4 c/w (junction-to-case) * where the ambient temperature rating (t amb ) is: t amb = t case ?(pd ca ) t case = case temperature in c pd = power dissipation in w power dissipation to determine total power dissipation in a specific application, the following equation should be applied for each output: cv f dd 2 c = load capacitance, f = output switching frequency. example: in an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows:
rev. 0 SST-MELODY-DAP ?9? 1/t ck e mhz 50 power (p int ) e mw 55 60 110 115 v dd e 2.65v v dd e 2.5v v dd e 2.35v 82mw 70mw 61mw 110mw 95mw 82mw 100 105 90 95 80 85 70 75 60 65 55 65 70 75 80 power, internal 1, 2, 3 1/t ck e mhz 50 power (p idle ) e mw 55 60 v dd e 2.65v v dd e 2.5v v dd e 2.35v 24mw 16.5mw 28mw 24mw 20mw 14 65 70 75 80 20mw 16 18 20 22 24 26 28 30 power, idle 1, 2, 4 1/t ck e mhz 50 power (p idle n ) e mw 55 60 24mw 12 65 70 75 80 14 16 18 20 22 24 26 16.4mw 15.7mw 20mw 15mw 14.25mw idle idle (16) idle (128) power, idle n modes 2 notes va lid for all temperature grades. 1 power reflects device operating with no output loads. 2 typical power dissipation at 2.5v v didint and 25 c, except where specified. 3 ido measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 20% are type 2 and type 6, and 20% are idle instructions. 4 idle refers to state of operating during execution of idle instruction. deasserted pins are driven to either v dd or gnd. figure 2. power vs. frequency capacitive loading figures 3 and 4 show the capacitive loading characteristics of the SST-MELODY-DAP. c l ?pf 0 rise time (0.4v?.4v) ?ns 50 100 0 150 200 250 300 15 20 25 30 10 5 t = 85 c v dd = 0v to 2.0v figure 3. typical output rise time vs. load capacitance (at maximum ambient operating temperature) c l ?pf 0 va l id output delay or hold ?ns 50 100 ? 150 200 250 6 10 14 18 2 ? 4 8 12 16 nominal ? figure 4. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature)
rev. 0 ?10? SST-MELODY-DAP executive kernel input stream output stream decoding library software architecture the SST-MELODY-DAP software programming model has the following parts: ? executive kernel ? algorithm suite as library modules the executive kernel has the following functions: ? power-up hardware initialization ? serial port management ? automatic stream detect ? automatic code load ? command processing ? interrupt handling ? data buffer management ? calling library module ? status report the executive kernel is executed as soon as booting takes place. the hardware resources are initialized in the beginning. the ?ommand buffer?and general-purpose programmable flag pins are initialized. various data buffers and memory variables are initialized. interrupts are programmed and enabled. then defi- nite signatures are written ?ommand buffer?to inform the host that adsp is ready to receive the commands. once commands are issued by host micro, these are executed and appropriate action takes place. decoding is handled by issuing appropriate commands by host micro. the kernel communicates with the library module for a particu- lar algorithm in a definite way. the details are found in the specific implementation documents. architecture overview the SST-MELODY-DAP instruction set provides flexible data moves and multifunction (one or two data moves with a com- putation) instructions. every instruction can be executed in a single processor cycle. the SST-MELODY-DAP assembly lan guage uses an algebraic syntax for ease of coding and readability. a comprehensive set of development tools supports program development. a functional block diagram of the SST-MELODY-DAP is pro- vided. the processor contains three independent computational units: the alu, the multiplier/accumulator (mac), and the shifter. the computational units process 16-bit data directly and have provisions to support multiprecision computations. the alu performs a standard set of arithmetic and logic opera- tions; division primitives are also supported. the mac performs single-cycle multiply, multiply/add, and multiply/subtract opera- tions with 40 bits of accumulation. the shifter performs logical and arithmetic shifts, normalization, denormalization, and de- rive exponent operations. the shifter can be used to efficiently implement numeric format control, including multiword and block floating-point representations. the internal result (r) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu- tational units. the sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. with internal loop counters and loop stacks, the SST-MELODY-DAP executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is postmodified by the value of one of four possible modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. efficient data transfer is achieved with the use of five internal buses: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? result (r) bus
rev. 0 SST-MELODY-DAP ?11? the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip. the two databuses (pmd and dmd) share a single external databus. byte memory space and i/o memory space also share the external buses. program memory can store both instructions and data, permit- ting the SST-MELODY-DAP to fetch two operands in a single cycle, one from program memory and one from data memory. the SST-MELODY-DAP can fetch an operand from program memory and the next instruction in the same cycle. in lieu of the address and databus for external memory connection, the SST-MELODY-DAP may be configured for 16-bit internal dma port (idma port) connection to external systems. the idma port is made up of 16 data/address pins and five control pins. the idma port provides transparent, direct access to the dsp? on-chip program and data ram. an interface to low cost byte-wide memory is provided by the byte dma port (bdma port). the bdma port is bidirectional and can directly address up to four megabytes of external ram or rom for off-chip storage of program overlays or data tables. the byte memory and i/o memory space interface supports slow memories and i/o memory-mapped peripherals with pro- grammable wait state generation. external devices can gain control of external buses with bus request/grant signals (br, bgh, and bg). one execution mode (go mode) allows the SST-MELODY-DAP to continue running from on-chip memory. normal execution mode requires the processor to halt while buses are granted. the SST-MELODY-DAP can respond to 11 interrupts. there can be up to six external interrupts (one edge-sensitive, two level- sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (sports), the byte dma port, and the power-down circuitry. there is also a mas- ter reset signal. the two serial ports provide a complete synchronous serial interface with optional companding in hard- ware and a wide variety of framed or frameless data transmit and receive modes of operation. each port can generate an internal programmable serial clock or accept an external serial clock. the SST-MELODY-DAP provides up to 13 general-purpose flag pins. the data input and output pins on sport1 can be alternatively configured as an input flag and an output flag. in addition, eight flags are programmable as inputs or out- puts, and three flags are always outputs. a programmable interval timer generates periodic interrupts. a 16-bit count register (tcount) decrements every n pro- cessor cycle, where n is a scaling value stored in an 8-bit register (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). serial ports the SST-MELODY-DAP incorporates two complete synchronous serial ports (sport0 and sport1) for serial communications and multiprocessor communication. here is a brief list of the capabilities of the SST-MELODY-DAP sports: ? sports are bidirectional and have a separate, double buff- ered transmit and receive section. ? sports can use an external serial clock or generate their own serial clock internally. ? sports have independent framing for the receive and trans- mit sections. sections run in a frameless mode or with frame synchronization signals internally or externally generated. frame sync signals are active high or inverted, with either of two pulsewidths and timings. ? sports support serial data-word lengths from three to 16 bits and provide optional a-law and -law companding according to ccitt recommendation g.711. ? sport receive and transmit sections can generate unique interrupts on completing a data-word transfer. ? sports can receive and transmit an entire circular buffer of data with only one overhead cycle per data-word. an inter- rupt is generated after a data buffer transfer. ? sport0 has a multichannel interface to selectively receive and transmit a 24- or 32-word, time-division multiplexed, serial bitstream. ? sport1 can be configured to have two external interrupts (irq0 and irq1) and the fi and fo signals. the internally generated serial clock may still be used in this configuration. pin descriptions the SST-MELODY-DAP is available in a 100-lead lqfp package and a 144-ball mini-bga package. in order to maintain maxi- mum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt, and external bus pins have dual multiplexed functionality. the external bus pins are configured during reset only, while serial port pins are soft- ware configurable during program execution. flag and interrupt functionality is retained concurrently on multiplexed pins. in cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics.
rev. 0 ?12? SST-MELODY-DAP common-mode pins mnemonic no. of pins i/o function reset 1i processor reset input br 1i bus request input bg 1o bus grant output bgh 1o bus grant hung output dms 1o data memory select output pms 1o program memory select output ioms 1o memory select output bms 1o byte memory select output cms 1o combined memory select output rd 1o memory read enable output wr 1o memory write enable output irq2 1i edge- or level-sensitive interrupt request 1 pf7 i/o programmable i/o pin irql1 1i level-sensitive interrupt requests 1 pf6 i/o programmable i/o pin irql0 1i level-sensitive interrupt requests 1 pf5 i/o programmable i/o pin irqe 1i edge-sensitive interrupt requests 1 pf4 i/o programmable i/o pin mode d 1 i mode select input?hecked only during reset pf3 i/o programmable i/o pin during normal operation mode c 1 i mode select input?hecked only during reset pf2 i/o programmable i/o pin during normal operation mode b 1 i mode select input?hecked only during reset pf1 i/o programmable i/o pin during normal operation mode a 1 i mode select input?hecked only during reset pf0 i/o programmable i/o pin during normal operation clkin, xtal 2 i clock or quartz crystal input clkout 1 o processor clock output sport0 5 i/o serial port i/o pins sport1 5 i/o serial port i/o pins irq1 : irq0 , fi, fo edge- or level-sensitive interrupts, fi, fo 2 pwd 1i power-down control input pwdack 1 o power-down control output fl0, fl1, fl2 3 o output flags v ddint 2i internal v dd (2.5 v) power (lqfp) v ddext 4i external v dd (2.5 v or 3.3 v) power (lqfp) gnd 10 i ground (lqfp) v ddint 4i internal v dd (2.5 v) power (mini-bga) v ddext 7i external v dd (2.5 v or 3.3 v) power (mini-bga) gnd 20 i ground (mini-bga) ez-port 9 i/o for emulation use notes 1 interrupt/flag pins retain both functions concurrently. if imask is set to enable the corresponding interrupts, then the dsp wi ll vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag. 2 sport configuration determined by the dsp system control register. software configurable.
rev. 0 SST-MELODY-DAP ?13? full memory mode pins (mode c = 0) mnemonic no. of pins i/o function a13:0 14 o address output pins for program, data, byte, and i/o spaces d23:0 24 i/o data i/o pins for program, data, byte, and i/o spaces (8 msbs are also used as byte memory addresses) host mode pins (mode c = 1) mnemonic no. of pins i/o function iad15:0 16 i/o idma port address/data bus a0 1 o address pin for external i/o, program, data, or byte access * d23:8 16 i/o data i/o pins for program, data, byte, and i/o spaces iwr 1i idma write enable ird 1i idma read enable ial 1 i idma address latch pin is 1i idma select iack 1o idma port acknowledge configurable in mode d; open drain * in host mode, external peripheral addresses can be decoded using the a0, cms , pms , dms , and ioms signals. memory interface pins the SST-MELODY-DAP processor can be used in one of two modes: full memory mode, which allows bdma operation with full exter- nal overlay memory and i/o capability, or host mode, which allows idma operation with limited external addressing capabilities. the operating mode is determined by the state of the mode c pin during reset and cannot be changed while the processor is running. the following tables list the active signals at specific pins of the dsp during either of the two operating modes (full memory or host). a signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode set . for the shared pins and their alternate signals (e.g., a4/iad3), refer to the package pinout tables. table iv. pin terminations 1, 2, 3, 4 table iv shows the recommendations for terminating unused pins. i/o three-state reset hi-z 5 mnemonic (z) state caused by unused configuration xtal i i float clkout o o float a13:1 or o (z) hi-z br , ebr float iad 12:0 i/o (z) hi-z is float a0 o (z) hi-z br , ebr float d23:8 i/o (z) hi-z br , ebr float d7 or i/o (z) hi-z br , ebr float iwr ii high (inactive) d6 or i/o (z) hi-z br , ebr float ird ii br , ebr high (inactive) d5 or i/o (z) hi-z float ial i i low (inactive) d4 or i/o (z) hi-z br , ebr float is ii high (inactive) d3 or i/o (z) hi-z br , ebr float iack float d2:0 or i/o (z) hi-z br , ebr float iad15:13 i/o (z) hi-z is float
rev. 0 ?14? SST-MELODY-DAP table iv. pin terminations (continued) i/o three-state reset hi-z 5 mnemonic (z) state caused by unused configuration pms o (z) o br , ebr float dms o (z) o br , ebr float bms o (z) o br , ebr float ioms o (z) o br , ebr float cms o (z) o br , ebr float rd o (z) o br , ebr float wr o (z) o br , ebr float br ii high (inactive) bg o (z) o ee float bgh oo fl oat irq2/ pf7 i/o (z) i input = high (inactive) or program as output, set to 1, let float irql1 /pf6 i/o (z) i input = high (inactive) or program as output, set to 1, let float irql0 /pf5 i/o (z) i input = high (inactive) or program as output, set to 1, let float irqe /pf4 i/o (z) i input = high (inactive) or program as output, set to 1, let float sclk0 i/o i input = high or low, output = float rfs0 i/o i high or low dr0 i i high or low tfs0 i/o i high or low dt0 o o float sclk1 i/o i input = high or low, output = float rfs1/ irq0 i/o i high or low dr1/fi i i high or low tfs1/ irq1 i/o i high or low dt1/fo o o float ee i i float ebr ii fl oat ebg oo fl oat ereset ii fl oat ems oo fl oat eint ii fl oat eclk i i float elin i i float elout o o float notes 1 if the clkout pin is not used, turn it off using clkodis in sport0 autobuffer control register. 2 if the interrupt/programmable flag pins are not used, there are two options: option 1: when these pins are configured as inputs at reset and function as interrupts and input flag pins, pull the pins high (inactive). option 2: program the unused pins as outputs, set them to 1 prior to enabl ing interrupts, and let pins float. 3 all bidirectional pins have three-stated outputs. when the pin is configured as an output, the output is hi-z (high impedance) when inactive. 4 clkin, reset, and pf3:0/mode d:a are not included in the table because these pins must be used. 5 hi-z = high impedance.
rev. 0 SST-MELODY-DAP ?15? interrupts the interrupt controller allows the processor to respond to the 11 possible interrupts and reset with minimum overhead. the SST-MELODY-DAP provides four dedicated external interrupt input pins: irq2 , irql0 , irql1 , and irqe (shared with the pf7:4 p ins). in addition, sport1 may be reconfigured for irq0 , irq1 , fi, and fo, for a total of six external interrupts. the SST-MELODY-DAP also supports internal interrupts from the timer, the byte dma port, the two serial ports, software, and the power-down control circuit. the interrupt levels are internally prioritized and individually maskable (except power- down and reset ). the irq2 , irq0 , and irq1 input pins can be pro grammed to be either level- or edge-sensitive. irql0 and irql1 are level-sensitive and irqe is edge-sensitive. the priori- ties and vector addresses of all interrupts are shown in table v. table v. interrupt priority and interrupt vector addresses interrupt vector source of interrupt address (hex) reset (or power-up with pucr = 1) 0000 (highest priority) power-down (nonmaskable) 002c irq2 0004 irql1 0008 irql0 000c sport0 transmit 0010 sport0 receive 0014 irqe 0018 bdma interrupt 001c sport1 transmit or irq1 0020 sport1 receive or irq0 0024 timer 0028 (lowest priority) interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. inter- rupts can be masked or unmasked with the imask register. individual interrupt requests are logically anded with the bits in imask; the highest priority unmasked interrupt is then selected. the power-down interrupt is nonmaskable. the SST-MELODY-DAP masks all interrupts for one instruction cycle following the execution of an instruction that modifies the imask register. this does not affect serial port autobuffering or dma transfers. the interrupt control register, icntl, controls interrupt nest- ing and defines the irq0 , irq1 , and irq2 external interrupts to be either edge or level-sensitive. the irqe pin is an external edge-sensitive interrupt and can be forced and cleared. the irql0 a nd irql1 pins are external level-sensitive interrupts. the ifc register is a write-only register used to force and clear interrupts. on-chip stacks preserve the processor status and are automatically maintained during interrupt handling. the stacks are 12 levels deep to allow interrupt, loop, and subroutine nesting. the following instructions allow global enable or dis- able servicing of the interrupts (including power-down), regardless of the state of imask. disabling the interrupts does not affect serial port autobuffering or dma. ena ints; dis ints; when the processor is reset, interrupt servicing is enabled. low power operation the SST-MELODY-DAP has three low power modes that signifi- cantly reduce the power dissipation when the device operates under standby conditions. these modes are: ? power-down ? idle ? slow idle the clkout pin may also be disabled to reduce external power dissipation. power-down the SST-MELODY-DAP processor has a low power feature that lets the processor enter a very low power dormant state through hardware or software control. following is a brief list of power- down features. refer to the adsp-2100 family user? manual , ?ystem interface?chapter, for detailed information about the power-down feature. ? quick recovery from power-down. the processor begins executing instructions in as few as 200 clkin cycles. ? support for an externally generated ttl or cmos processor clock. the external clock can continue running during power- down without affecting the lowest power rating and 200 clkin cycle recovery. ? support for crystal operation includes disabling the oscillator to save power (the processor automatically waits approxi- mately 4096 clkin cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to allow 200 clkin cycle startup. ? power-down is initiated by either the power-down pin (pwd) or the software power-down force bit. interrupt support allows an unlimited number of instructions to be executed before optionally powering down. the power-down interrupt also can be used as a nonmaskable, edge-sensitive interrupt. ? context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state. ? the reset pin also can be used to terminate power-down. ? power-down acknowledge pin indicates when the processor has entered power-down. idle when the SST-MELODY-DAP is in the idle mode, the processor waits indefinitely in a low power state until an interrupt occurs. when an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the idle instruction. in idle mode, idma, bdma, and autobuffer cycle steals still occur. slow idle the idle instruction is enhanced on the SST-MELODY-DAP to let the processor? internal clock signal be slowed, further reducing power consumption. the reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the idle instruction. the format of the instruction is: idle (n); where n = 16, 32, 64, or 128. this instruction keeps the proces- sor fully functional, but operating at the slower clock rate. while it is in this state, the processor? other internal clock signals
rev. 0 ?16? SST-MELODY-DAP full memory mode host memory mode SST-MELODY-DAP 1/2x clock or crystal clkin xtal fl0e2 irq2 p irqe p irql0 p irql1 p moded p modec p2 modea p0 modeb p1 addr10 da t a20 bms wr rd ioms pms dms cms br bg bgh pwd pw dack sport1 sclk1 rs1 irq0 ts1 irq1 dt1o serial deice serial deice dr1i sport0 sclk0 rs0 ts0 dt0 dr0 sstmdap 12clock or crstal sport1 sclk1 rs1 irq0 ts1 irq1 dt1o serial deice dr1i serial deice sport0 sclk0 rs0 ts0 dt0 dr0 pms dms cms br bg bgh pwd pw dack d ird d iwr d is dial d iack iad10 idmaport sstem interace or controller 1 irq2 p irqe p irql0 p irql1 p moded p modec p2 modea p0 modeb p1 clkin tal l02 1 1 1 2 a0a21 data cs bte memor addr data cs iospace peripherals 200locations addr data o erla memor twok pmsegments twok dmsegments a0 da t a20 bms wr rd ioms a 10 d 21 d 10 a 100 d 20 a 10 d 20 bsi (such as sclk, clkout) and timer clock are reduced by the same ratio. the default form of the instruction, when no clock divisor is given, is the standard idle instruction. when the idle (n) instruction is used, it effectively slows down the processor? internal clock and thus its response time to incoming interrupts. the one-cycle response time of the standard idle state is increased by n, the clock divisor. when an enabled interrupt is received, the SST-MELODY-DAP will remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming normal operation. when the idle (n) instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the processor? reduced internal clock rate. under these conditions, interrupts must not be generated at a faster than can be serviced rate, due to the additional time the pro cessor takes to come out of the idle state (a maximum of n processor cycles). system interface figure 5 shows typical basic system configurations with the SST-MELODY-DAP, two serial devices, a byte-wide eprom, and optional external program and data overlay memories (mode- selectable). programmable wait state generation allows the processor to connect easily to slow peripheral devices. the SST-MELODY-DAP also provides four external interrupts and two serial ports or six external interrupts and one serial port. host memory mode allows access to the full external databus, but limits addressing to a single address bit (a0). through the use of external hardware, additional system peripherals can be added in this mode to generate and latch address signals. clock signals the SST-MELODY-DAP can be clocked by either a crystal or a ttl compatible clock signal. the clkin input cannot be halted, changed during operation, nor operated below the specified frequency during normal operation. the only exception is while the processor is in the power-down state. if an external clock is used, it should be a ttl compatible signal running at half the instruction rate. the signal is con- nected to the processor? clkin input. when an external clock is used, the xtal input must be left unconnected. the SST-MELODY-DAP uses an input clock with a frequency equal to half the instruction rate; a 37.50 mhz input clock yields a 13 ns processor cycle (which is equivalent to 75 mhz). normally, instructions are executed in a single processor cycle. all device timing is relative to the internal instruction clock rate, which is indicated by the clkout signal when enabled. because the SST-MELODY-DAP includes an on-chip oscillator circuit, an external crystal may be used. the crystal should be connected across the clkin and xtal pins, with two capacitors connected as shown in figure 6. capacitor values are dependent
rev. 0 SST-MELODY-DAP ?17? mode d mode c mode b mode a booting method bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in full memory mode. * no automatic boot operations occur. program execution starts at external memory location 0. chip is configured in full memory mode. bdma can still be used, but the processor does not automatically use or wait for these operations. bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in host mode; iack has active pull-down (requires additional hardware). idma feature is used to load any internal memory as desired. program execution is held off until internal program memory location 0 is written to. chip is configured in host mode. iack has active pull-down. * bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in host mode; iack requires external pull- down (requires additional hardware). idma feature is used to load any internal memory as desired. program execution is held off until internal program memory location 0 is written to. chip is configured in host mode. iack requires external pull down. * * considered standard operating settings. using these configurations allows for easier design and better memory management. table vi. modes of operation x x 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 1 on crystal type and should be specified by the crystal manufac- turer. a parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. a clock output (clkout) signal is generated by the processor at the processor? cycle rate. this can be enabled and disabled by the clkodis bit in the sport0 autobuffer control register. clkin xtal clkout dsp figure 6. external crystal connections reset the reset signal initiates a master reset of the sst-melody- dap. the reset signal must be asserted during the power-up sequence to assure proper initialization. reset during initial power-up must be held long enough to allow the internal clock to stabilize. if reset is activated any time after power-up, the clock continues to run and does not require stabilization time. the power-up sequence is defined as the total time required for the crystal oscillator circuit to stabi- lize after a valid vdd is applied to the processor, and for the internal phase-locked loop (pll) to lock onto the specific crys- tal frequency. a minimum of 2000 clkin cycles ensures that the pll has locked but does not include the crystal oscillator start-up time. during this power-up sequence, the reset signal should be held low. on any subsequent resets, the reset signal must meet the minimum pulsewidth specification, t rsp . the reset input contains some hysteresis; however, if an rc circuit is used to generate the reset signal, the use of an external schmitt trigger is recommended. the master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and clears the mstat register. when reset is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. the first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes. power supplies the SST-MELODY-DAP has separate power supply connections for the internal (vddint) and external (vddext) power sup- plies. the internal supply must meet the 2.5 v requirement. the external supply can be connected to either a 2.5 v or 3.3 v supply. all external supply pins must be connected to the same supply. all input and i/o pins can tolerate input voltages up to 3.6 v, regard- less of the external supply voltage. this feature provides maximum flexibility in mixing 2.5 v and 3.3 v components. modes of operation setting memory mode memory mode selection for the SST-MELODY-DAP is made during chip reset through the use of the mode c pin. this pin is multi plexed with the dsp? pf2 pin, so care must be taken in how the mode selection is made. the two methods for selecting the value of mode c are active and passive. passive configuration passive configuration involves the use of a pull-up or pull-down resistor connected to the mode c pin. to minimize power
rev. 0 ?18? SST-MELODY-DAP pm (mode b = 0) pm (mode b = 1) 1 always a ccessible at address 0x0000 e 0x1fff a ccessible when pmovlay = 0 reserved a ccessible when pmovlay = 0 a ccessible when pmovlay = 1 a ccessible when pmovlay = 2 0x2000 e 0x3fff 0x2000 e 0x3fff 2 0x2000 e 0x3fff 2 external memory program memory mode b = 0 address 8k internal pmovlay = 0 or 8k external pmovlay = 1, 2 8k internal 8k external 0x3fff 0x2000 0x0000 0x1fff 8k internal pmovlay = 0 0x3fff 0x2000 0x0000 0x1fff program memory mode b = 1 address 0x2000 e 0x3fff 0x0000 e 0x1fff 2 0x0000 e 0x1fff 2 external memory notes 1 when mode b = 1, pmovlay must be set to 0 2 see table vii for pmovlay bits a ccessible when pmovlay = 0 reserved consumption, or if the pf2 pin is to be used as an output in the dsp application, a weak pull-up or pull-down, on the order of 10 k ? , can be used. this value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a program- mable flag output without undue strain on the processor? output driver. for minimum power consumption during power-down, reconfigure pf2 to be an input, as the pull-up or pull-down will hold the pin in a known state, and will not switch. active configuration active configuration involves the use of a three-statable exter nal driver connected to the mode c pin. a driver? output enable should be connected to the dsp? reset signal such that it only drives the pf2 pin when reset is active low. when reset is deasserted, the driver should three-state, thus allowing full use of the pf2 pin as either an input or output. to minimize power consumption during power-down, configure the programmable flag as an output when connected to a three- stated buffer. this ensures that the pin will be held at a constant level and will not oscillate should the three-state driver? level hover around the logic switching point. pmovlay memory a13 a12:0 0 internal not applicable not applicable 1 external overlay 1 0 13 lsbs of address between 0x2000 and 0x3fff 2 external overlay 2 1 13 lsbs of address between 0x2000 and 0x3fff table vii. pmovlay bits figure 7. program memory
rev. 0 SST-MELODY-DAP ?19? * see table viii for dmovlay bits da ta memory always a ccessible at address 0x2000 e 0x3fff a ccessible when dmovlay = 0 a ccessible when dmovlay = 1 a ccessible when dmovlay = 2 32 memory mapped registers internal 8160 words 0x3fff 0x3fe0 0x3fdf 0x2000 0x1fff 0x0000 8k internal dmovlay = 0 or external 8k dmovlay = 1, 2 da ta memory addr external memory 0x0000e0x1fff 0x0000e0x1fff * 0x0000e0x1fff * figure 8. program memory table viii. dmovlay bits program memory program memory (full memory mode) is a 24-bit wide space for storing both instruction opcodes and data. the sst-melody- dap has 16k words of program memory ram on-chip, and the capability of accessing up to two 8k external memory overlay spaces using the external databus. program memory (host mode) allows access to all internal memory. external overlay access is limited by a single external address line (a0). external program execution is not available in host mode due to a restricted databus that is 16 bits wide only. data memory data memory (full memory mode) is a 16-bit wide space used for the storage of data variables and for memory-mapped con- trol registers. the SST-MELODY-DAP has 16k words on d ata memory ram on-chip. part of this space is used by 32 memory-mapped registers. support also exists for up to two 8k external memory overlay spaces through the external databus. all internal accesses complete in one cycle. accesses to external memory are timed using the wait states specified by the dwait register and the wait state mode bit. 1 11 1111111111111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w ait state control w ait state mode select 0 = normal mode (pwait, dwait, iowait0? ?n wait states, ranging from 0 to 7) 1 = 2n + 1 mode (pwait, dwait, iowait0? ?2n + 1 wait states, ranging from 0 to 15) dw ait iowait3 iowait2 iowait1 iowait0 dm(0 3ffe) figure 9. wait state control register 1 11 1101100000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 programmable flag and composite select control bmwait dm(0 3fe6) cmssel 0 = disable cms 1enable cms ptpe 0inpt 1otpt wherebit11iom10bmdmpm 10pc cr dmola m a1 a120 0 internal not applicable not applicable 1 external overlay 1 0 13 lsbs of address between 0x2000 and 0x3fff 2 external overlay 2 1 13 lsbs of address between 0x2000 and 0x3fff iack c mode d = 0 and in host mode, iack is an active, driven signal and cannot be ?ire-ored. mode d = 1 and in host mode, iack is an open drain and requires an external pull-down, but multiple iack pins can be ?ire-ored?together. memory architecture the SST-MELODY-DAP provides a variety of memory and pe- ripheral interface options. the key functional groups are p rogram memory, data memory, byte memory, and i/o. refer to the following figures and tables for pm and dm memory allocations in the SST-MELODY-DAP.
rev. 0 ?20? SST-MELODY-DAP memory-mapped registers (new to the SST-MELODY-DAP) the SST-MELODY-DAP has three memory-mapped registers that differ from other adsp-21xx family dsps. the slight modifications to these registers (wait state control, program- mable flag and composite select control, and system control) provide the SST-MELODY-DAP? wait state and bms control features. default bit values at reset are shown; if no value is shown, the bit is undefined at reset. reserved bits are shown on a gray field. these bits should always be written with zeros. data memory (host mode) allows access to all internal memory. external overlay access is limited by a single external address line (a0). 0 00 0010000000111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 system control dm(0 3fff) reserved set to 0 reserved, always set to 0 pwait program memory wait s tat e s sport0 enable 0 = disable 1 = enable sport1 enable 0 = disable 1 = enable sport1 configure 0 = fi, fo, irq0 irq1 sclk 1sport1 disable bms 0enable bms 1disable bms eceptwhenmemor strobesarethreestated reseredbitsareshownonagraieldthesebitsshold alwas bewrittenwith eros 11scr iosmm the SST-MELODY-DAP supports an additional external memory space called i/o space. this space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface asic data registers. i/o space supports 2048 locations of 16-bit wide data. the lower 11 bits of the external address bus are used; the upper three bits are undefined. two instructions were added to the core adsp-2100 family instruction set to read from and write to i/o memory space. the i/o space also has four dedicated 3-bit wait state registers, iowait0?, which in combination with the wait state mode bit specify up to 15 wait states to be automatically gener- ated for each of four regions. the wait states act on address ranges as shown in table ix. table ix. wait states address range wait state register 0x000?x1ff iowait0 and wait state mode select bit 0x200?x1ff iowait1 and wait state mode select bit 0x400?x1ff iowait2 and wait state mode select bit 0x600?x1ff iowait3 and wait state mode select bit composite memory select ( cms the SST-MELODY-DAP has a programmable memory select signal that is useful for generating memory select signals for memo ries mapped to more than one space. the cms signal is generated to have the same timing as each of the individual memory select signals ( pms , dms , bms , ioms ) but can combine their functionality. each bit in the cmssel register, when set, causes the cms signal to be asserted when the selected memory select is asserted. for example, to use a 32k word memory to act as both program and data memory, set the pms and dms bits in the cmssel register and use the cms pin to drive the chip select of the memory, and use either dms or pms as the addi- tional address bit. the cms pin functions like the other memory select signals with the same timing and bus request logic. a ??in the enable bit causes the assertion of the cms signal at the same time as the selected memory select signal. all enable bits default to 1 at reset, except the bms bit. byte memory select ( bms the SST-MELODY-DAP? bms disable feature, combined with the cms pin, allows use of multiple memories in the byte memory space. for example, an eprom could be attached to the bms select, and an sram could be connected to cms. because bms is enabled at reset, the eprom would be used for boot ing. after booting, software could disable bms and set the cms signal to respond to bms , enabling the sram. byte memory the byte memory space is a bidirectional, 8-bit wide, external memory space used to store programs and data. byte memory is accessed using the bdma feature. the byte memory space consists of 256 pages, each of which is 16k 8. the byte memory space on the SST-MELODY-DAP supports read and write operations as well as four different data formats. the byte memory uses data bits 15:8 for data. the byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. this allows up to a 4 meg 8 (32 megabit) rom or ram to be used without glue logic. all byte memory accesses are timed by the bmwait register and the wait state mode bit. byte memory dma (bdma, full memory mode) the byte memory dma controller allows loading and storing of program instructions and data using the byte memory space. the bdma circuit is able to access the byte memory space while the processor is operating normally and steals only one dsp cycle per 8-, 16-, or 24-bit word transferred. 0 00 0000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bdma control dm(0 3fe3) bmpage btype bdir 0 = load from bm 1 = store to bm bcr 0 = run during bdma 1 = halt during bdma bdma o verlay bits figure 12. bdma control register the bdma circuit supports four different data formats that are selected by the btype register field. the appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. table x shows the data formats sup- ported by the bdma circuit.
rev. 0 SST-MELODY-DAP ?21? table x. data formats btype internal memory space word size alignment 00 program memory 24 full word 01 data memory 16 full word 10 data memory 8 msbs 11 data memory 8 lsbs unused bits in the 8-bit data memory formats are filled with 0s. the biad register field is used to specify the starting address for the on-chip memory involved with the transfer. the 14-bit bead register specifies the starting address for the external byte memory space. the 8-bit bmpage register specifies the starting page for the external byte memory space. the bdir register field selects the direction of the transfer. finally, the 14- bit bwcount register specifies the number of dsp words to transfer and initiates the bdma circuit transfers. bdma accesses can cross page boundaries during sequential addressing. a bdma interrupt is generated on the completion of the number of transfers specified by the bwcount register. the bwcount register is updated after each transfer so it can be used to check the status of the transfers. when it reaches zero, the transfers have finished and a bdma interrupt is generated. the bmpage and bead registers must not be accessed by the dsp during bdma operations. the source or destination of a bdma transfer will always be on-chip program or data memory. when the bwcount register is written with a nonzero value, the bdma circuit starts executing byte memory accesses with wait states set by bmwait. these accesses continue until the count reaches zero. when enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. the transfer takes one dsp cycle. dsp accesses to external memory have priority over bdma byte memory accesses. the bdma context reset bit (bcr) controls whether the processor is held off while the bdma accesses are occurring. setting the bcr bit to 0 allows the processor to continue opera- tions. setting the bcr bit to 1 causes the processor to stop execution while the bdma accesses are occurring, to clear the context of the processor, and start execution at address 0 when the bdma accesses have completed. the bdma overlay bits specify the ovlay memory blocks to be accessed for internal memory. for SST-MELODY-DAP, set to zero bdma overlay bits in the bdma control register. the bmwait field, which has four bits on SST-MELODY-DAP, allows selection up to 15 wait states for bdma transfers. internal memory dma port (idma port; host memory mode) the idma port provides an efficient means of communication between a host system and the SST-MELODY-DAP. the port is used to access the on-chip program memory and data memory of the dsp with only one dsp cycle per word overhead. the idma port cannot, however, be used to write to the dsp? memory-mapped control registers. a typical idma transfer process is described as follows: 1. host starts idma transfer 2. host checks iack control line to see if the dsp is busy 3. host uses is and ial control lines to latch either the dma starting address (idmaa) or the pm/dm ovlay selection into the dsp? idma control registers. if bit 15 = 1, the value of bits 7:0 represent the idma overlay and bits 14:8 must be set to 0. if bit 15 = 0, the value of bits 13:0 represent the starting address of internal memory to be accessed and bit 14 reflects pm or dm for access. for SST-MELODY-DAP, iddmovlay and idpmovlay bits in the idma overlay register should be set to zero. 4. host uses is and ird (or iwr ) to read (or write) dsp internal memory (pm or dm). 5. host checks iack line to see if the dsp has completed the previous idma operation. 6. host ends idma transfer. the idma port has a 16-bit multiplexed address and databus and supports 24-bit program memory. the idma port is completely asynchronous and can be written while the SST-MELODY-DAP is operating at full speed. the dsp memory address is latched and then automatically incremented after each idma transaction. an external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. this increases throughput as the address does not have to be sent for each memory access. idma port access occurs in two phases. the first is the idma address latch cycle. when the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. the address specifies an on-chip memory location, the destination type specifies whether it is a dm or pm access. the falling edge of the idma address latch signal (ial) or the missing edge of the idma select signal ( is ) latches this value into the idmaa register. once the address is stored, data can be read from or written to, the SST-MELODY-DAP? on-chip memory. asserting the select line ( is ) and the appropriate read or write line ( ird and iwr respectively) signals the SST-MELODY-DAP that a particular transaction is required. in either case, there is a one processor cycle delay for synchronization. the memory access consumes one additional processor cycle. once an access has occurred, the latched address is automati- cally incremented, and another access can occur. through the idmaa register, the dsp can also specify the starting address and data format for dma operation. asserting the idma port select ( is ) and address latch enable (ial) directs the SST-MELODY-DAP to write the address onto the iad 0?4 bus into the idma control register. if bit 15 is set to 0, idma latches the address. if bit 15 is set to 1, idma latches into the ovlay register. this register, shown in figure 13, is memory- mapped at address dm (0x3fe0). note that the latched address (idmaa) cannot be read back by the host. for sst-melody- dap, iddmovlay and idpmovlay bits in the idma overlay register should be set to 0. refer to the following figures for more information on idma and dma memory maps.
rev. 0 ?22? SST-MELODY-DAP dma program memory o vlay always a ccessible at address 0x0000 e 0x1fff a ccessible when pmovlay = 0 0x2000 e 0x3fff dma da ta memory o vlay always a ccessible at address 0x2000 e 0x3fff a ccessible when dmovlay = 0 0x0000 e 0x1fff idma and sdma have separate dma control registers. 0 00 0000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 idma overlay reserved set to 0 dm(0x3fe7) iddmovlay idpmovlay short read only 0 = enable 1 = disable reserved set to 0 0 uu uuuuuuuuuuuuu 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 idma control (u = undefined at reset) dm(0x3fe70) idmaa address idmad destination memory type 0 = pm 1 = dm reserved set to 0 reserved bits are shown on a gray field. these bits should always be written with zeros. figure 13. idma control/ovlay registers figure 14. direct memory access??pm and dm memory maps bootstrap loading (booting) the SST-MELODY-DAP has two mechanisms to allow automatic loading of the internal program memory after reset. the method for booting is controlled by the mode a, b, and c configura- tion bits. when the mode pins specify bdma booting, the sst-melody- dap initiates a bdma boot sequence when reset is released. the bdma interface is set up during reset to the following defaults when bdma booting is specified: the bdir, bmpage, biad, and bead registers are set to 0, the btype register is set to 0 to specify program memory 24-bit words, and the bwcount register is set to 32. this causes 32 words of on-chip program memory to be loaded from byte memory. these 32 words are used to set up the bdma to load in the remaining program code. the bcr bit is also set to 1, which causes program execu- tion to be held off until all 32 words are loaded into on-chip program memory. execution then begins at address 0. the idle instruction can also be used to allow the processor to hold off execution while booting continues through the bdma interface. for bdma accesses while in host mode, the addresses to boot memory must be constructed externally to the sst- melody-dap. the only memory address bit provided by the processor is a0. idma port booting the SST-MELODY-DAP can also boot programs through its internal dma port. if mode c = 1, mode b = 0, and mode a = 1, the SST-MELODY-DAP boots from the idma port. the idma feature can load as much on-chip memory as desired. program execution is held off until on-chip program memory location 0 is written to. bus request and bus grant the SST-MELODY-DAP can relinquish control of the data and address buses to an external device. when the external device requires access to memory, it asserts the bus request ( br ) signal. if the SST-MELODY-DAP is not performing an external memory access, it responds to the active br input in the following processor cycle by: ? three-stating the data and address buses and the pms , dms , bms , cms , ioms , rd , and wr output drivers, ? asserting the bus grant ( bg ) signal, and ? halting program execution. if go mode is enabled, the SST-MELODY-DAP will not halt program execution until it encounters an instruction that requires an external memory access. if the SST-MELODY-DAP is performing an external memory access when the external device asserts the br signal, it will not three-state the memory interfaces nor assert the bg signal until the processor cycle after the access completes. the instruction does not need to be completed when the bus is granted. if a single instruction requires two external memory accesses, the bus will be granted between the two accesses. when the br signal is released, the processor releases the bg signal, re-enables the output drivers, and continues program execution from the point at which it stopped. the bus request feature operates at all times, including when the processor is booting and when reset is active. the bgh pin is asserted when the SST-MELODY-DAP requires the external bus for a memory or bdma access, but is stopped. the other device can release the bus by deasserting the bus request. once the bus is released, the SST-MELODY-DAP deasserts bg and bgh and executes the external memory access. flag i/o pins the SST-MELODY-DAP has eight general-purpose program- mable input/output flag pins. they are controlled by two memory-mapped registers. the pftype register determines the direction: 1 = output and 0 = input. the pfdata register is used to read and write the values on the pins. data being read from a pin configured as an input is synchronized to the SST-MELODY-DAP? clock. bits that are programmed as outputs will read the value being output. the pf pins default to input during reset. in addition to the programmable flags, the SST-MELODY-DAP has five fixed-mode flags, fi, fo, fl0, fl1, and fl2. fl0?l2 are dedicated output flags. fi and fo are available as an alternate configuration of sport1. note: pins pf0, pf1, pf2, and pf3 are also used for device configuration during reset.
rev. 0 SST-MELODY-DAP ?23? outline dimensions dimensions shown in millimeters 100-lead quad flatpack [lqfp] (st-100) top view (pins down) 1 25 26 51 50 75 76 100 14.00 bsc sq 0.50 bsc 0.27 0.22 0.17 1.60 max seating plane 12 typ 0.75 0.60 0.45 view a 7 3.5 0 0.15 0.05 0.08 max lead coplanarity seating plane view a rotated 90 ccw 0.20 0.09 16.00 bsc sq 12.00 ref compliant to jedec standards ms-026bed the actual position of each lead is within 0.08 of its ideal position when measured in the lateral direction
c03010?0?10/02(0) printed in u.s.a. ?24?

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